The design of random-testable sequential circuits

In general, sequential circuits are considered not to be random-testable. since a required lest sequence may grow exponentially with the number of f1ipflops. and it is very unlikely that a certain sequence occurs at random. This problem can be solved by combining tWO tasks: I) A small pan of the f1ipflops are made directly accessible, for instance by a partial scan path or by a built-in self-test register. 2) Weighted random patterns are applied to the modified sequential circuit. The paper describes a method to select a minimal set of flip-flops as mentioned in 1). Since this problem turns out to be NP-complete, suboptimal solutions can be derived using some heuristics. Furthermore, an algorithm is presented to compute the corresponding weights of the patterns, which are time-dependent in some cases. Finally the entire approach is validated with the help of examples. Only 10% 40% of the flip-nops have to be integrated into a panial scan path or into a BIST-register in order to obtain nearly complete fault coverage by weighted random patterns .